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<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\impl\gwsynthesis\top.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\src\top.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>F:\code\fpga\MIC_HDMI_FINISHED\src\lcd.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Nov 20 04:37:02 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>757.981</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>168.387</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>589.594</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>49.271</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>60.729</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Use Vectorless Estimation</td>
<td>false</td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>511.412</td>
<td>104.222</td>
<td>615.634</td>
</tr>
<tr>
<td>VCCX</td>
<td>2.500</td>
<td>13.614</td>
<td>23.366</td>
<td>92.450</td>
</tr>
<tr>
<td>VCCO15</td>
<td>1.500</td>
<td>11.074</td>
<td>1.867</td>
<td>19.411</td>
</tr>
<tr>
<td>VCCO25</td>
<td>2.500</td>
<td>0.196</td>
<td>0.106</td>
<td>0.755</td>
</tr>
<tr>
<td>VCCO33</td>
<td>3.300</td>
<td>8.195</td>
<td>0.814</td>
<td>29.730</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>Logic</td>
<td>10.486</td>
<td>NA</td>
<td>6.024</td>
</tr>
<tr>
<td>IO</td>
<td>108.029
<td>15.552
<td>44.548
</tr>
<tr>
<td>BSRAM</td>
<td>310.326
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>PLL</td>
<td>78.060
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>DLL</td>
<td>92.160
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>DQS</td>
<td>231.300
<td>NA</td>
<td>NA</td>
</tr>
<tr>
<td>DSP</td>
<td>5.844
<td>NA</td>
<td>1.946
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>top</td>
<td>728.176</td>
<td>728.176(728.143)</td>
<tr>
<td>top/Btn_Control_inst1/</td>
<td>0.045</td>
<td>0.045(0.044)</td>
<tr>
<td>top/Btn_Control_inst1/Btn_Sample_Clk_inst/</td>
<td>0.044</td>
<td>0.044(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/</td>
<td>457.443</td>
<td>457.443(457.443)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/</td>
<td>457.443</td>
<td>457.443(457.443)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/</td>
<td>455.862</td>
<td>455.862(363.333)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr3_sync/</td>
<td>0.058</td>
<td>0.058(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/</td>
<td>0.583</td>
<td>0.583(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/</td>
<td>362.692</td>
<td>362.692(362.685)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/</td>
<td>246.704</td>
<td>246.704(246.696)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/</td>
<td>115.655</td>
<td>115.655(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_in_fifo/</td>
<td>65.520</td>
<td>65.520(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/</td>
<td>65.521</td>
<td>65.521(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/</td>
<td>115.659</td>
<td>115.659(115.651)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/</td>
<td>115.651</td>
<td>115.651(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/</td>
<td>0.219</td>
<td>0.219(0.154)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_cmd_fifo/</td>
<td>0.154</td>
<td>0.154(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/</td>
<td>0.103</td>
<td>0.103(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/</td>
<td>1.580</td>
<td>1.580(1.320)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/</td>
<td>0.320</td>
<td>0.320(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_rd_data0/</td>
<td>0.195</td>
<td>0.195(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/</td>
<td>0.307</td>
<td>0.307(0.305)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/</td>
<td>0.305</td>
<td>0.305(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gwmc_bank_ctrl/</td>
<td>0.376</td>
<td>0.376(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gwmc_rank_ctrl/</td>
<td>0.088</td>
<td>0.088(0.000)</td>
<tr>
<td>top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gwmc_timing_ctrl/</td>
<td>0.034</td>
<td>0.034(0.000)</td>
<tr>
<td>top/DVI_TX_Top_inst/</td>
<td>0.473</td>
<td>0.473(0.473)</td>
<tr>
<td>top/DVI_TX_Top_inst/rgb2dvi_inst/</td>
<td>0.473</td>
<td>0.473(0.473)</td>
<tr>
<td>top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/</td>
<td>0.157</td>
<td>0.157(0.000)</td>
<tr>
<td>top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/</td>
<td>0.159</td>
<td>0.159(0.000)</td>
<tr>
<td>top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/</td>
<td>0.157</td>
<td>0.157(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/</td>
<td>35.360</td>
<td>35.360(35.314)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/ahb_interface/</td>
<td>0.016</td>
<td>0.016(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/core/</td>
<td>3.992</td>
<td>3.992(2.054)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/core/pcpi_div/</td>
<td>0.219</td>
<td>0.219(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/core/pcpi_mul/</td>
<td>1.835</td>
<td>1.835(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/dtcm/</td>
<td>15.408</td>
<td>15.408(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/itcm/</td>
<td>15.410</td>
<td>15.410(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/</td>
<td>0.131</td>
<td>0.131(0.106)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/cleardebint_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/dm_debint_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/dm_haltnot_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/dm_hartid_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/sethaltnot_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dbg_irq_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dbg_irq_sync/sync_gen[1].i_is_not_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/</td>
<td>0.008</td>
<td>0.008(0.007)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_dat_dfflr/</td>
<td>0.006</td>
<td>0.006(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/buf_vld_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/i_rdy_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/i_vld_sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/</td>
<td>0.007</td>
<td>0.007(0.006)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/buf_nrdy_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/dat_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/o_rdy_sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/u_o_rdy_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/u_o_rdy_sync/sync_gen[0].i_is_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/u_o_rdy_sync/sync_gen[1].i_is_not_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm2dtm_cdc_tx/vld_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/</td>
<td>0.003</td>
<td>0.003(0.003)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/</td>
<td>0.003</td>
<td>0.003(0.003)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_0/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_10/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_11/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_12/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_13/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_14/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_15/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_16/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_17/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_18/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_19/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_2/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_3/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_4/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_5/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_6/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_7/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_8/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_dm_RstSync_2_1/reset_n_catch_reg/reg_9/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_jtag_RstSync_3_1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_jtag_RstSync_3_1/reset_n_catch_reg/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_jtag_RstSync_3_1/reset_n_catch_reg/reg_0/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_jtag_RstSync_3_1/reset_n_catch_reg/reg_1/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_jtag_RstSync_3_1/reset_n_catch_reg/reg_2/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/</td>
<td>0.019</td>
<td>0.019(0.010)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/dcause_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/dpc_dfflr/</td>
<td>0.004</td>
<td>0.004(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/dscratch_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/ebreakm_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/halt_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_csr/step_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/</td>
<td>0.069</td>
<td>0.069(0.032)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[0].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[1].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[2].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[3].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[4].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[5].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_debug_ram/debug_ram_gen[6].ram_dfflr/</td>
<td>0.005</td>
<td>0.005(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/buf_dat_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/buf_vld_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/i_rdy_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/i_vld_sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/u_i_vld_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/u_i_vld_sync/sync_gen[0].i_is_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_rx/u_i_vld_sync/sync_gen[1].i_is_not_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/buf_nrdy_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/dat_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/o_rdy_sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/u_o_rdy_sync/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/u_o_rdy_sync/sync_gen[0].i_is_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/u_o_rdy_sync/sync_gen[1].i_is_not_0.sync_dffr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/u_dm/u_s_jtag_dtm/u_jtag2debug_cdc_tx/vld_dfflr/</td>
<td>0.000</td>
<td>0.000(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wb/</td>
<td>0.016</td>
<td>0.016(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wb_intercon/</td>
<td>0.002</td>
<td>0.002(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wbuart_ins/</td>
<td>0.340</td>
<td>0.340(0.309)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wbuart_ins/rx/</td>
<td>0.156</td>
<td>0.156(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wbuart_ins/rxfifo/</td>
<td>0.052</td>
<td>0.052(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wbuart_ins/tx/</td>
<td>0.064</td>
<td>0.064(0.000)</td>
<tr>
<td>top/Gowin_PicoRV32_Top_inst/wbuart_ins/txfifo/</td>
<td>0.037</td>
<td>0.037(0.000)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/</td>
<td>116.746</td>
<td>116.746(116.746)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/</td>
<td>116.746</td>
<td>116.746(116.746)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/</td>
<td>116.453</td>
<td>116.453(116.453)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/</td>
<td>0.019</td>
<td>0.019(0.000)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/</td>
<td>54.318</td>
<td>54.318(54.199)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/</td>
<td>54.153</td>
<td>54.153(0.000)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/</td>
<td>0.046</td>
<td>0.046(0.000)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/</td>
<td>62.116</td>
<td>62.116(62.023)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/</td>
<td>61.961</td>
<td>61.961(0.000)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/</td>
<td>0.062</td>
<td>0.062(0.000)</td>
<tr>
<td>top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/</td>
<td>0.293</td>
<td>0.293(0.000)</td>
<tr>
<td>top/ahb_communicate_inst/</td>
<td>0.038</td>
<td>0.038(0.000)</td>
<tr>
<td>top/cmos_8_16bit_m0/</td>
<td>0.021</td>
<td>0.021(0.000)</td>
<tr>
<td>top/cmos_pll_m0/</td>
<td>2.510</td>
<td>2.510(0.000)</td>
<tr>
<td>top/i2c_config_m0/</td>
<td>0.280</td>
<td>0.280(0.268)</td>
<tr>
<td>top/i2c_config_m0/i2c_master_top_m0/</td>
<td>0.268</td>
<td>0.268(0.081)</td>
<tr>
<td>top/i2c_config_m0/i2c_master_top_m0/byte_controller/</td>
<td>0.081</td>
<td>0.081(0.065)</td>
<tr>
<td>top/i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/</td>
<td>0.065</td>
<td>0.065(0.000)</td>
<tr>
<td>top/max_sample_inst/</td>
<td>0.022</td>
<td>0.022(0.000)</td>
<tr>
<td>top/mem_pll_m0/</td>
<td>41.658</td>
<td>41.658(0.000)</td>
<tr>
<td>top/mic_serial_inst/</td>
<td>0.284</td>
<td>0.284(0.157)</td>
<tr>
<td>top/mic_serial_inst/mic_sample_inst1/</td>
<td>0.058</td>
<td>0.058(0.000)</td>
<tr>
<td>top/mic_serial_inst/mic_sample_inst2/</td>
<td>0.041</td>
<td>0.041(0.000)</td>
<tr>
<td>top/mic_serial_inst/mic_sample_inst3/</td>
<td>0.058</td>
<td>0.058(0.000)</td>
<tr>
<td>top/steer_inst1/</td>
<td>0.162</td>
<td>0.162(0.000)</td>
<tr>
<td>top/steer_inst2/</td>
<td>0.163</td>
<td>0.163(0.000)</td>
<tr>
<td>top/syn_gen_inst/</td>
<td>0.093</td>
<td>0.093(0.000)</td>
<tr>
<td>top/u_tmds_rpll/</td>
<td>33.891</td>
<td>33.891(0.000)</td>
<tr>
<td>top/vitual_image_inst/</td>
<td>1.923</td>
<td>1.923(0.000)</td>
<tr>
<td>top/xcorr1/</td>
<td>9.259</td>
<td>9.259(8.226)</td>
<tr>
<td>top/xcorr1/mic_data_store_inst1/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr1/mic_data_store_inst1/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr1/mic_data_store_inst2/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr1/mic_data_store_inst2/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr2/</td>
<td>9.257</td>
<td>9.257(8.226)</td>
<tr>
<td>top/xcorr2/mic_data_store_inst1/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr2/mic_data_store_inst1/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr2/mic_data_store_inst2/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr2/mic_data_store_inst2/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr3/</td>
<td>9.259</td>
<td>9.259(8.226)</td>
<tr>
<td>top/xcorr3/mic_data_store_inst1/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr3/mic_data_store_inst1/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr3/mic_data_store_inst2/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr3/mic_data_store_inst2/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr4/</td>
<td>9.258</td>
<td>9.258(8.226)</td>
<tr>
<td>top/xcorr4/mic_data_store_inst1/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr4/mic_data_store_inst1/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
<tr>
<td>top/xcorr4/mic_data_store_inst2/</td>
<td>4.113</td>
<td>4.113(4.107)</td>
<tr>
<td>top/xcorr4/mic_data_store_inst2/Gowin_SDPB_inst2/</td>
<td>4.107</td>
<td>4.107(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>clk</td>
<td>27.000</td>
<td>151.075</td>
</tr>
<tr>
<td>DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk</td>
<td>100.000</td>
<td>200.031</td>
</tr>
<tr>
<td>u_clkdiv/CLKOUT.default_gen_clk</td>
<td>64.800</td>
<td>24.045</td>
</tr>
<tr>
<td>cmos_16bit_clk</td>
<td>100.000</td>
<td>29.181</td>
</tr>
<tr>
<td>steer_inst1/clk_50hz_6</td>
<td>100.000</td>
<td>0.150</td>
</tr>
<tr>
<td>steer_inst2/clk_50hz_6</td>
<td>100.000</td>
<td>0.149</td>
</tr>
<tr>
<td>cmos_pclk</td>
<td>100.000</td>
<td>0.030</td>
</tr>
<tr>
<td>NO CLOCK DOMAIN</td>
<td>0.000</td>
<td>0.000</td>
</tr>
<tr>
<td>max_finish</td>
<td>100.000</td>
<td>0.076</td>
</tr>
<tr>
<td>cmos_vsync</td>
<td>1.000</td>
<td>0.000</td>
</tr>
<tr>
<td>mic_clk_d</td>
<td>100.000</td>
<td>0.044</td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst2/clk_cnt_0[1]</td>
<td>100.000</td>
<td>0.031</td>
</tr>
<tr>
<td>mic_serial_inst/mic_sample_inst3/clk_cnt_0[1]</td>
<td>100.000</td>
<td>0.044</td>
</tr>
<tr>
<td>u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>324.000</td>
<td>0.044</td>
</tr>
<tr>
<td>mem_clk</td>
<td>400.000</td>
<td>323.514</td>
</tr>
</table>
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